89HPES6T5集成電路（IC）的專用規(guī)格書PDF中文資料

Features

u High Performance PCI Express Switch

– Six 2.5Gbps PCI Express lanes

– Five switch ports

– Upstream port is x2

– Downstream ports are x1

– Low-latency cut-through switch architecture

– Support for Max Payload Sizes up to 256 bytes

– One virtual channel

– Eight traffic classes

– PCI Express Base Specification Revision 1.1 compliant

u Flexible Architecture with Numerous Configuration Options

– Automatic lane reversal on all ports

– Automatic polarity inversion

– Ability to load device configuration from serial EEPROM

u Legacy Support

– PCI compatible INTx emulation

– Bus locking

u Highly Integrated Solution

– Requires no external components

– Incorporates on-chip internal memory for packet buffering and

queueing

– Integrates six 2.5 Gbps embedded SerDes with 8B/10B

encoder/decoder (no separate transceivers needed)

u Reliability, Availability, and Serviceability (RAS) Features

– Internal end-to-end parity protection on all TLPs ensures data

integrity even in systems that do not implement end-to-end

CRC (ECRC)

– Supports ECRC and Advanced Error Reporting

– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O

– Compatible with Hot-Plug I/O expanders used on PC motherboards

u Power Management

– Utilizes advanced low-power design techniques to achieve low

typical power consumption

– Support PCI Power Management Interface specification (PCIPM

1.2)

– Unused SerDes are disabled.

– Supports Advanced Configuration and Power Interface Specification,

Revision 2.0 (ACPI) supporting active link state

u Testability and Debug Features

– Built in Pseudo-Random Bit Stream (PRBS) generator

– Numerous SerDes test modes

– Ability to read and write any internal register via the SMBus

– Ability to bypass link training and force any link into any mode

– Provides statistics and performance counters