8A34046集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

Typical Applications

? Core and access IP switches / routers

? Synchronous Ethernet equipment

? 10Gb, 40Gb, and 100Gb Ethernet interfaces

? Wireless infrastructure for 4.5G and 5G network equipment

? OTN muxponders and line cards

Features

? Compliant with G.8262 option 1 and option 2, and G.8262.1

? Supports ITU-T G.709 frequencies

? Meets OTN jitter and wander requirements per ITU-T G.8251

? Four independent DPLL/DCO channels

? Each can act as a frequency synthesizer, jitter attenuator,

Digitally Controlled Oscillator (DCO), or Digital Phase Lock

Loop (DPLL)

? DPLL Digital Loop Filters (DLFs) are programmable with

cut-off frequencies from 0.1Hz to 22kHz

? Each DPLL generates an output frequency via a Fractional

Output Divider (FOD)

? Each FOD supports output phase tuning with 50ps

resolution

? Four independent DCO channels

? Each DCO generates an independent output frequency via a

Fractional Output Divider (FOD)

? DPLL/DCO and DCO channels can be configured as Satellite

Channels that increase the number of independently

programmable FODs and output stages available to other

DPLL/DCO or DCO channels