8P73S674集成電路（IC）的時鐘緩沖器驅動器規(guī)格書PDF中文資料

General Description

The 8P73S674 is a 1.8V LVPECL Clock Divider and Fanout Buffer.

The device has been designed for clock signal division and fanout in

wireless base station (radio and base band), high-end computing and

telecommunication equipment. The device is optimized to deliver

excellent phase noise performance. The 8P73S674 uses SiGe

technology for an optimum of high clock frequency and low phase

noise performance, combined with high power supply noise rejection.

The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four

low-skew 1.8V LVPECL outputs are available for and support clock

output frequencies up to 1GHz (÷1 frequency division). 1.8V LVPECL

outputs are terminated 50? to GND. Outputs can be disabled to save

power consumption if not used. The device is packaged in a lead-free

(RoHS 6) 20-lead VFQFN package. The extended temperature range

supports wireless infrastructure, telecommunication and networking

end equipment requirements. The device is a member of the

high-performance clock family from IDT.

Features

? Clock signal division and distribution

? SiGe technology for high-frequency and fast signal rise/fall times

? Four low-skew LVPECL clock outputs

? Supports frequency division of ÷1, ÷2, ÷4 and ÷8

? Maximum Output frequency: 1GHz

? Output skew: 100ps (maximum)

? LVPECL output rise/fall time (20 - 80): 220ps (maximum)

? 1.8V core and output supply mode

? Supports 1.8V I/O LVCMOS logic levels for all control pins

? -40°C to +85°C ambient operating temperature

? Lead-free (RoHS 6) 20-lead VFQFN packaging