8S89200中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

General Description

The 8S89200 is a high speed 1-to-8 Differential-to-LVDS Clock

Divider and is part of the high performance clock solutions from IDT.

The 8S89200 is optimized for high speed and very low output skew,

making it suitable for use in demanding applications such as SONET,

1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally

terminated differential inputs and VREF_AC pins allow other

differential signal families such as LVPECL, LVDS and CML to be

easily interfaced to the input with minimal use of external

components.

The device also has a selectable ÷1, ÷2, ÷4 output divider, which can

allow the part to support multiple output frequencies from the same

reference clock.

The 8S89200 is packaged in a small 5mm x 5mm 32-pin VFQFN

package which makes it ideal for use in space-constrained

applications.

Features

? Three output banks, consisting of eight LVDS output pairs total

? INx, nINx inputs can accept the following differential input levels:

LVPECL, LVDS, CML

? Selectable output divider values of ÷1, ÷2 and ÷4

? Maximum output frequency: 1.5GHz

? Maximum input frequency: 3GHz

? Bank Skew: 10ps (typical)

? Part-to-part skew: 100ps (typical)

? Additive phase jitter, RMS: 0.170ps (typical)

? Propagation delay: 802ps (typical)

? Output rise time: 150ps (typical)

? 2.5V±5 operating supply voltage

? -40°C to 85°C ambient operating temperature

? Available in lead-free (RoHS 6) package