Description

The 8SLVD1204 is a high-performance differential LVDS fanout

buffer. The device is designed for the fanout of high-frequency, very

low additive phase-noise clock and data signals. The 8SLVD1204 is

characterized to operate from a 2.5V power supply. Guaranteed

output-to-output and part-to-part skew characteristics make the

8SLVD1204 ideal for those clock distribution applications demanding

well-defined performance and repeatability.

Two selectable differential inputs and four low skew outputs are

available. The integrated bias voltage reference enables easy

interfacing of single-ended signals to the device inputs. The device is

optimized for low power consumption and low additive phase noise.

Features

? Four low skew, low additive jitter LVDS output pairs

? Two selectable differential clock input pairs

? Differential PCLK, nPCLK pairs can accept the following

differential input levels: LVDS, LVPECL

? Maximum input clock frequency: 2GHz

? LVCMOS/LVTTL interface levels for the control input select pin

? Output skew: 20ps (maximum)

? Propagation delay: 300ps (maximum)

? Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,

10kHz - 20MHz: 95fs (maximum)

? Full 2.5V supply voltage

? Lead-free (RoHS 6), 16-Lead VFQFPN packaging

? Supports case temperature ≤ 105°C operations

? -40°C to 85°C ambient operating temperature

8SLVD1204屬于集成電路（IC） > 時(shí)鐘緩沖器，驅(qū)動(dòng)器。瑞薩科技有限公司制造生產(chǎn)的8SLVD1204時(shí)鐘緩沖器，驅(qū)動(dòng)器時(shí)鐘緩沖器和驅(qū)動(dòng)器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時(shí)間參考信號，以同步系統(tǒng)內(nèi)的活動(dòng)。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅(qū)動(dòng)負(fù)載的影響而從某個(gè)信號源復(fù)制信號），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個(gè)整數(shù)值分割信號頻率，或進(jìn)行所用電信號格式轉(zhuǎn)換。