8SLVP1102集成電路（IC）的時鐘緩沖器驅(qū)動器規(guī)格書PDF中文資料

Description

The 8SLVP1102 is a high-performance differential LVPECL fanout

buffer. The device is designed for the fanout of high-frequency, very

low additive phase-noise clock and data signals. The 8SLVP1102 is

characterized to operate from a 3.3V or 2.5V power supply.

Guaranteed output-to-output and part-to-part skew characteristics

make the 8SLVP1102 ideal for those clock distribution applications

demanding well-defined performance and repeatability. One

differential input and two low skew outputs are available. The

integrated bias voltage reference enables easy interfacing of

single-ended signals to the device input. The device is optimized for

low power consumption and low additive phase noise.

Features

? Two low skew, low additive jitter LVPECL output pairs

? Differential PCLK, nPCLK pair can accept the following differential

input levels: LVDS, LVPECL, CML

? Maximum input clock frequency: 2GHz

? Output skew: 5ps (typical)

? Propagation delay: 250ps (maximum)

? Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,

12kHz–20MHz: 49fs (maximum)

? Full 3.3V or 2.5V supply voltage

? Maximum device current consumption (IEE): 34mA (maximum)

? Available in lead-free (RoHS 6), 16-Lead VFQFPN package

? -40°C to +85°C ambient operating temperature

? Supports case temperature ≤ 105°C operations

? Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also

accept single-ended LVCMOS levels. See Applications section

Wiring the Differential Input Levels to Accept Single-ended Levels

(Figure 1A and Figure 1B)

? Supports PCI Express Gen1–5