8T33FS6221ETGI集成電路（IC）的時鐘緩沖器驅(qū)動器規(guī)格書PDF中文資料

Description

The 8T33FS6221 is a bipolar monolithic differential clock fanout

buffer. Designed for most demanding clock distribution systems, the

8T33FS6221 supports various applications that require the

distribution of precisely aligned differential clock signals. Using SiGe

technology and a fully differential architecture, the device offers very

low skew outputs and superior digital signal characteristics. Target

applications for this clock driver is high performance clock

distribution in computing, networking and telecommunication

systems.

The 8T33FS6221 is designed for low skew clock distribution

systems and supports clock frequencies up to 2GHz. The device

accepts two clock sources. The CLK0 input can be driven by PECL

compatible signals, the CLK1 input accepts HSTL compatible

signals. The selected input signal is distributed to 20 identical,

differential PECL outputs. If VBB is connected to the nCLK0 or

nCLK1 input and bypassed to GND by a 10nF capacitor, the

8T33FS6221 can be driven by single-ended PECL signals utilizing

the VBB bias voltage output.

In order to meet the tight skew specification of the device, both

outputs of a differential output pair should be terminated, even if only

one output is used. In the case where not all ten outputs are used,

the output pairs on the same package side as the parts being used

on that side should be terminated.

The 8T33FS6221 can be operated from a single 3.3V or 2.5V supply

Features

? 1:20 differential clock fanout buffer

? 50ps typical device skew

? SiGe technology

? Maximum output frequency: 2GHz

? PECL compatible differential clock outputs

? PECL/ HSTL compatible differential clock inputs

? Single 3.3V or 2.5V supply

? Standard 52 lead LQFP package with exposed pad for enhanced

thermal characteristics

? Supports industrial temperature range

? Lead-free Packaging