8T49N240-DDDNLGI8中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Description

The 8T49N240 is a fractional-feedback single channel jitter

attenuator with frequency translation. It is equipped with three

integer and one fractional output dividers, allowing the generation

of up to four different output frequencies, ranging from 8kHz to

867MHz. These frequencies are completely independent of the

input reference frequencies and the crystal reference frequency.

The outputs may select among LVPECL, LVDS, HCSL, or

LVCMOS output levels.

The 8T49N240 accepts up to two differential or single-ended input

clocks and a fundamental-mode crystal input. The internal PLL

can lock to either of the input reference clocks or just to the crystal

to behave as a frequency synthesizer. The PLL can use the

second input for redundant backup of the primary input reference,

but in this case, both input clock references must be integer

related in frequency.

The device supports hitless reference switching between input

clocks. The device monitors both input clocks for Loss of Signal

(LOS), and generates an alarm when an input clock failure is

detected. Automatic and manual hitless reference switching

options are supported. LOS behavior can be set to support

gapped or un-gapped clocks.

The 8T49N240 supports holdover. The holdover has an initial

accuracy of ±50ppB from the point where the loss of all applicable

input reference(s) has been detected. It maintains a historical

average operating point for the PLL that may be returned to in

holdover at a limited phase slope.

The PLL has a register-selectable loop bandwidth from 0.2Hz to

6.4kHz.

The device supports Output Enable and Clock Select inputs and

Lock, Holdover, and LOS status outputs.

The device is programmable through an I2

C interface. It also

supports I2

C master capability to allow the register configuration

to be read from an external EEPROM.

Factory pre-programmed devices are also available using the

on-chip One Time Programmable (OTP) memory.

Features

? Four differential outputs

? Excellent jitter performance:

— < 200fs (typical) RMS (including spurs):

12kHz to 20MHz for integer-divider outputs in jitter

attenuator mode or in fractional-feedback synthesizer mode

? Operating Modes: Synthesizer, Jitter Attenuator

? Operates from a 10MHz to 54MHz fundamental-mode crystal

? Initial holdover accuracy of +50ppb

? Accepts up to two LVPECL, LVDS, LVHSTL, or LVCMOS input

clocks

— Accepts frequencies ranging from 8kHz to 875MHz

— Auto and manual clock selection with hitless switching

— Clock input monitoring including support for gapped clocks

? Phase-slope limiting and fully hitless switching options to

control output clock phase transients

? Three outputs generate LVPECL / LVDS / HCSL clocks, one

output generates LVPECL / LVDS / HCSL / LVCMOS clocks

— Output frequencies ranging from 8kHz up to 867MHz

(differential)

— Output frequencies ranging from 8kHz to 250MHz

(LVCMOS)

— Three integer dividers with fixed divider ratios (see Table 3)

— One fractional output divider

? Programmable loop bandwidth settings from 0.2Hz to 6.4kHz

— Optional fast-lock function

? Four General Purpose I/O pins with optional support for status

and control:

— Two Output Enable control inputs provide control over the

four clocks

— Manual clock selection control input

— Lock, Holdover, and Loss-of-Signal alarm outputs

? Open-drain Interrupt pin

? Register programmable through I2

C or via external I2

C

EEPROM

? Full 2.5V or 3.3V supply modes, with some support for 1.8V

? -40°C to 85°C ambient operating temperature

? Package: 6 x 6 x 0.9 mm 40-VFQFN, lead-free (RoHS 6)