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8T49N281集成電路(IC)的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

8T49N281
廠商型號

8T49N281

參數(shù)屬性

8T49N281 封裝/外殼為56-VFQFN 裸露焊盤;包裝為托盤;類別為集成電路(IC)的時鐘發(fā)生器PLL頻率合成器;產(chǎn)品描述:VFQFPN 8.00X8.00X0.85 MM, 0.50MM

功能描述

FemtoClock? NG Octal Universal Frequency Translator

封裝外殼

56-VFQFN 裸露焊盤

文件大小

1.67384 Mbytes

頁面數(shù)量

64

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標識
數(shù)據(jù)手冊

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更新時間

2025-2-25 20:42:00

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8T49N281規(guī)格書詳情

Description

The 8T49N281 has a fractional-feedback PLL that can be used as a

jitter attenuator or frequency translator. It is equipped with six integer

and two fractional output dividers, allowing the generation of up to 8

different output frequencies, ranging from 8kHz to 1GHz. Three of

these frequencies are completely independent of each other and the

inputs. The other five are related frequencies. The eight outputs may

select among LVPECL, LVDS or LVCMOS output levels.

This functionality makes it ideal to be used in any frequency

translation application, including 1G, 10G, 40G and 100G

Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T

G.709 (2009) FEC rates. The device may also behave as a frequency

synthesizer.

The 8T49N281 accepts up to two differential or single-ended input

clocks and a crystal input. The PLL can lock to either input clock, but

both input clocks must be related in frequency.

The device supports hitless reference switching between input

clocks. The device monitors both input clocks for Loss of Signal

(LOS). It generates an alarm when an input clock failure is detected.

Automatic and manual hitless reference switching options are

supported. LOS behavior can be set to support gapped or un-gapped

clocks.

The 8T49N281 supports holdover with an initial accuracy of ±50ppB

from the point where the loss of all applicable input reference(s) has

been detected. It maintains a historical average operating point that

may be returned to in holdover at a limited phase slope.

The device places no constraints on input to output frequency

conversion, supporting all FEC rates, including the new revision of

ITU-T Recommendation G.709 (2009), most with 0ppm conversion

error.

The PLL has a register-selectable loop bandwidth from 0.5Hz to

512Hz.

Each output supports individual phase delay settings to allow

output-output alignment.

The device supports Output Enable inputs and Lock, Holdover and

LOS status outputs.

The device is programmable through an I2C interface. It also supports

I

2C master capability to allow the register configuration to be read

from an external EEPROM.

Features

? Supports SDH/SONET and Synchronous Ethernet clocks

including all FEC rate conversions

? Two differential outputs meet jitter limits for 100G Ethernet and

STM-256/OC-768

? <0.3ps RMS (including spurs): 12kHz to 20MHz

? All outputs <0.5ps RMS (including spurs) 12kHz to 20MHz

? Operating modes: locked to input signal, holdover and free-run

? Initial holdover accuracy of ±50ppb

? Accepts two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS

input clocks

? Accepts frequencies ranging from 8kHz up to 875MHz

? Auto and manual input clock selection with hitless switching

? Clock input monitoring, including support for gapped clocks

? Phase-Slope Limiting and Fully Hitless Switching options to

control output phase transients

? Operates from a 10MHz to 40MHz fundamental-mode crystal

? Generates eight LVPECL /LVDS or sixteen LVCMOS output

clocks

? Output frequencies ranging from 8kHz up to 1.0GHz (diff)

? Output frequencies ranging from 8kHz to 250MHz (LVCMOS)

? Four General Purpose I/O pins with optional support for status &

control:

? Four Output Enable control inputs may be mapped to any of the

eight outputs

? Lock, Holdover & Loss-of-Signal status outputs

? Open-drain Interrupt pin

? Programmable PLL bandwidth settings:

? 0.5Hz, 1Hz, 2Hz, 4Hz, 8Hz, 16Hz, 32Hz, 64Hz, 128Hz, 256Hz

or 512Hz

? Optional Fast Lock function

? Programmable output phase delays in steps as small as 16ps

? Register programmable through I2C or via external I2C EEPROM

? Bypass clock paths for system tests

? Power supply modes

VCC / VCCA / VCCO

3.3V / 3.3V / 3.3V

3.3V / 3.3V / 2.5V

3.3V / 3.3V / 1.8V (LVCMOS)

2.5V / 2.5V / 3.3V

2.5V / 2.5V / 2.5V

2.5V / 2.5V / 1.8V (LVCMOS)

? Power down modes support consumption as low as 1.5W (see

Power Dissipation and Thermal Considerations for details)

? -40°C to 85°C ambient operating temperature

? Package: 56QFN, lead-free RoHs (6)

產(chǎn)品屬性

  • 產(chǎn)品編號:

    8T49N281C-031NLGI8

  • 制造商:

    Renesas Electronics America Inc

  • 類別:

    集成電路(IC) > 時鐘發(fā)生器,PLL,頻率合成器

  • 系列:

    FemtoClock? NG

  • 包裝:

    托盤

  • 類型:

    頻率轉(zhuǎn)換器

  • PLL:

    帶旁路

  • 輸入:

    HCSL,LVCMOS,LVDS,LVHSTL

  • 輸出:

    LVCMOS,LVDS,LVPECL

  • 比率 - 輸入:

    2:8

  • 差分 - 輸入:

    是/是

  • 頻率 - 最大值:

    250MHz

  • 分頻器/倍頻器:

    是/無

  • 電壓 - 供電:

    2.375V ~ 2.625V,3.135V ~ 3.465V

  • 工作溫度:

    -40°C ~ 85°C(TA)

  • 安裝類型:

    表面貼裝型

  • 封裝/外殼:

    56-VFQFN 裸露焊盤

  • 供應(yīng)商器件封裝:

    56-VFQFPN(8x8)

  • 描述:

    VFQFPN 8.00X8.00X0.85 MM, 0.50MM

供應(yīng)商 型號 品牌 批號 封裝 庫存 備注 價格
IDT
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一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力
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6000
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320
十年專營原裝現(xiàn)貨,假一賠十
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22+
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6000
進口原裝 假一罰十 現(xiàn)貨
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