9DB401C集成電路（IC）的應用特定時鐘/定時規(guī)格書PDF中文資料

Description

The 9DB401C is a DB400 Version 2.0 Yellow Cover part with

PCI Express support. It can be used in PC or embedded

systems to provide outputs that have low cycle-to-cycle jitter

(50ps), low output-to-output skew (100ps), and are PCI Express

gen 1 compliant. The 9DB401C supports a 1 to 4 output

configuration, taking a spread or non spread differential HCSL

input from a CK410(B) main clock such as 954101 and

932S401, or any other differential HCSL pair. 9DB401C can

generate HCSL or LVDS outputs from 50 to 200MHz in PLL

mode or 0 to 400Mhz in bypass mode. There are two de-jittering

modes available selectable through the HIGH_BW# input pin,

high bandwidth mode provides de-jittering for spread inputs and

low bandwidth mode provides extra de-jittering for non-spread

inputs. The SRC_STOP#, PD#, and OE real-time input pins

provide completely programmable power management control.

Features/Benefits

? Spread spectrum modulation tolerant, 0 to -0.5 down

spread and +/- 0.25 center spread

? Supports undriven differential outputs in PD# and

SRC_STOP# modes for power management.