9DB633集成電路（IC）的應用特定時鐘/定時規(guī)格書PDF中文資料

General Description:

The 9DB633 zero-delay buffer supports PCIe Gen3

requirements, while being backwards compatible to PCIe

Gen2 and Gen1. The 9DB633 is driven by a differential SRC

output pair from an IDT 932S421 or 932SQ420 or equivalent

main clock generator. It attenuates jitter on the input clock

and has a selectable PLL bandwidth to maximize

performance in systems with or without Spread-Spectrum

clocking. An SMBus interface allows control of the PLL

bandwidth and bypass options, while 2 clock request (OE#)

pins make the 9DB633 suitable for Express Card

applications.

Features/Benefits:

? OE# pins/Suitable for Express Card applications

? PLL or bypass mode/PLL can dejitter incoming clock

? Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL's

? Spread Spectrum Compatible/tracks spreading input

clock for low EMI

? SMBus Interface/unused outputs can be disabled