9DB801CFLFT中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Key Specifications

? Outputs cycle-cycle jitter < 50ps

? Outputs skew: 50ps

? 50 - 200MHz operation

? Extended frequency range in bypass mode to 400 MHz

? PCI Express Gen I compliant

? Real time PLL lock detect output pin

? 48-pin SSOP/TSSOP package

? Available in RoHS compliant packaging

Features/Benefits

? Spread spectrum modulation tolerant, 0 to -0.5 down

spread and +/- 0.25 center spread.

? Supports undriven differential outputs in PD# and

SRC_STOP# modes for power management.

? Supports polarity inversion to the output enables,

SRC_STOP and PD.