9DBV0831集成電路（IC）的應(yīng)用特定時鐘/定時規(guī)格書PDF中文資料

Description

The 9DBV0831 is a member of Renesas’ SOC-Friendly 1.8V

Very-Low-Power (VLP) PCIe family. It can also be used for

50M or 125M Ethernet Applications via software frequency

selection. The device has 8 output enables for clock

management, and 3 selectable SMBus addresses.

Features/Benefits

? LP-HCSL outputs save 16 resistors; minimal board space

and BOM cost

? 62mW typical power consumption in PLL mode; minimal

power consumption

? Spread Spectrum (SS) compatible; allows use of SS for

EMI reduction

? OE# pins; support DIF power management

? HCSL compatible differential input; can be driven by

common clock sources

? Programmable Slew rate for each output; allows tuning for

various line lengths

? Programmable output amplitude; allows tuning for various

application environments

? Pin/software selectable PLL bandwidth and PLL Bypass;

minimize phase jitter for each application

? Outputs blocked until PLL is locked; clean system start-up

? Software selectable 50MHz or 125MHz PLL operation;

useful for Ethernet applications

? Configuration can be accomplished with strapping pins;

SMBus interface not required for device control

? 3.3V tolerant SMBus interface works with legacy controllers

? Space saving 6 x 6mm 48-VFQFPN; minimal board space

? Selectable SMBus addresses; multiple devices can easily

share an SMBus segment