9FGV1005CNNNLTGI8中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Features

? 1.8V to 3.3V power supplies

? Individual 1.8V to 3.3V VDDO for each output pair

? Supports HCSL, LVDS and LVCMOS I/O standards

? HCSL utilizes Renesas’ LP-HCSL technology for improved

performance, lower power and higher integration:

? Programmable output impedance of 85Ω or 100Ω

? Supports LVPECL and CML logic with easy AC coupling. See

application note AN-891 for alternate terminations

? On-board OTP supports up to 4 complete configurations

? Configuration selected via strapping pins or I2C

? Internal crystal load capacitors

? < 125mW at 1.8V, LP-HCSL outputs at 100MHz (9FGV1001C)

? < 100mW at 1.8V, LP-HCSL outputs at 100MHz (9FGV1005C)

? 4 programmable I2C addresses: D0, D2, D4, D6

? Easily configured with Renesas Timing Commander? software

or Web Configuration tool

? 4 × 4 mm 24-VFQFPN (9FGV1001)

? 3 × 3 mm 16-LGA (9FGV1005)

? Integrated crystal option available

Key Specifications

? 261fs RMS 12kHz–20MHz typical phase jitter at 156.25M Hz

? PCIe Gen5 jitter (CC) < 0.08ps RMS

? PCIe Gen5 jitter (SRNS)