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9LPR363YGLFT中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

9LPR363YGLFT
廠商型號(hào)

9LPR363YGLFT

功能描述

Low Power Programmable Timing Control Hub? for P4? processor

文件大小

287.46 Kbytes

頁(yè)面數(shù)量

21 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-27 13:00:00

9LPR363YGLFT規(guī)格書詳情

Recommended Application:

Low Power CK505 Compliant Main Clock

Output Features:

? 2 - 0.8V push-pull differential CPU pairs

? 7 - 0.8V push-pull differential PCIEX pairs

? 1 - 0.8V push-pull differential SATA pair

? 1 - 0.8V push-pull differential CPU/PCIEX selectable pair

? 1 - 0.8V push-pull differential 27MHz/LCDCLK/PCIEX

selectable pair

? 4 - PCI (33MHz)

? 2 - PCICLK_F, (33MHz) free-running

? 1 - USB, 48MHz

? 1 - DOT96/PCIEX selectable pair

? 2 - REF, 14.318MHz

Key Specifications:

? CPU outputs cycle-cycle jitter < 85ps

? PCIEX outputs cycle-cycle jitter < 125ps

? SATA outputs cycle-cycle jitter < 125ps

? PCI outputs cycle-cycle jitter < 500ps

? +/- 100ppm frequency accuracy on CPU, PCIEX and

SATA clocks

? +/- 100ppm frequency accuracy on USB clocks

Features/Benefits:

? Supports tight ppm accuracy clocks for Serial-ATA and

PCIEX

? Supports programmable spread percentage and

frequency

? Uses external 14.318MHz crystal, external crystal load

caps are required for frequency tuning

? PEREQ# pins to support PCIEX power management.

? Low power differential clock outputs (No 50Ω resistor

to GND needed)

? iAMT support

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23+
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10+
TSSOP64
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