9ZML1232BKLFT集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

Description

The 9ZML1232 is a 2-input/12-output differential mux for

use in servers. It meets the demanding DB1200ZL

performance specifications and utilizes Low-Power

HCSL-compatible outputs to reduce power consumption

and termination components. It is suitable for PCI-Express

Gen1–3 or QPI/UPI applications, and uses a fixed external

feedback to maintain low drift for demanding QPI

applications.

Applications

Clock Mux for Servers

Output Features

? 12 – Low-Power (LP) HCSL Output Pairs

Features

? 25MHz to 100MHz ZDB mode; supports PFT clock delay

management

? 9 selectable SMBus addresses; multiple devices can

share same SMBus segment

? Separate VDDIO for outputs; allows maximum power

savings

? PLL or bypass mode; PLL can dejitter incoming clock

? Hardware or software-selectable PLL BW; minimizes

jitter peaking in downstream PLLs

? Spread spectrum compatible; tracks spreading input

clock for EMI reduction

? SMBus interface; unused outputs can be disabled

? Differential outputs are Low/Low in power down;

maximum power savings

Key Specifications

? Cycle-to-cycle jitter < 50ps

? Output-to-output skew < 65ps

? Input-to-output delay: Fixed at 0ps

? Input-to-output delay variation < 50ps

? Phase jitter: PCIe Gen3 < 1ps rms

? Phase jitter: QPI/UPI 9.6GB/s