9ZX21901C集成電路（IC）的應(yīng)用特定時鐘/定時規(guī)格書PDF中文資料

Features/Benefits

? Fixed feedback path/ 0ps input-to-output delay

? 9 Selectable SMBus addresses; Multiple devices can share

same SMBus segment

? 8 dedicated OE# pins; hardware control of outputs

? PLL or bypass mode; PLL can dejitter incoming clock

? Selectable PLL BW; minimizes jitter peaking in downstream

PLL's

? Spread spectrum compatible; tracks spreading input clock

for EMI reduction

? SMBus Interface; unused outputs can be disabled

? 100MHz & 133.33MHz PLL mode; legacy QPI support

? Undriven differential outputs in Power Down mode for

maximum power savings