A3PE3000-1PQG208I中文資料美高森美數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

General Description

ProASIC3E, the third-generation family of Microsemi flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS? family. Nonvolatile flash technology gives ProASIC3E devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3E is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.

Features and Benefits

High Capacity

? 600 k to 3 Million System Gates

? 108 to 504 kbits of True Dual-Port SRAM

? Up to 620 User I/Os

Reprogrammable Flash Technology

? 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

? Instant On Level 0 Support

? Single-Chip Solution

? Retains Programmed Design when Powered Off

On-Chip User Nonvolatile Memory

? 1 kbit of FlashROM with Synchronous Interfacing

High Performance

? 350 MHz System Performance

? 3.3 V, 66 MHz 64-Bit PCI

In-System Programming (ISP) and Security

? ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

? FlashLock? Designed to Secure FPGA Contents

Low Power

? Core Voltage for Low Power

? Support for 1.5-V-Only Systems

? Low-Impedance Flash Switches

High-Performance Routing Hierarchy

? Segmented, Hierarchical Routing and Clock Structure

? Ultra-Fast Local and Long-Line Network

? Enhanced High-Speed, Very-Long-Line Network

? High-Performance, Low-Skew Global Network

? Architecture Supports Ultra-High Utilization

Pro (Professional) I/O

? 700 Mbps DDR, LVDS-Capable I/Os

? 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

? Bank-Selectable I/O Voltages—up to 8 Banks per Chip

? Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input

? Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS

? Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II

? I/O Registers on Input, Output, and Enable Paths

? Hot-Swappable and Cold Sparing I/Os

? Programmable Output Slew Rate and Drive Strength

? Programmable Input Delay

? Schmitt Trigger Option on Single-Ended Inputs

? Weak Pull-Up/-Down

? IEEE 1149.1 (JTAG) Boundary Scan Test

? Pin-Compatible Packages across the ProASIC?3E Family

Clock Conditioning Circuit (CCC) and PLL

? Six CCC Blocks, Each with an Integrated PLL

? Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback

? Wide Input Frequency Range (1.5 MHz to 350 MHz)

SRAMs and FIFOs

? Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)

? True Dual-Port SRAM (except ×18)

? 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz

ARM? Processor Support in ProASIC3E FPGAs

? M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available with or without Debug