A67L0618E中文資料歐密格數(shù)據(jù)手冊PDF規(guī)格書

General Description

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation.

The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers.

Features

■ Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz)

■ Zero Bus Latency between READ and WRITE cycles allows 100 bus utilization

■ Signal +3.3V ± 5 power supply

■ Individual Byte Write control capability

■ Clock enable ( CEN) pin to enable clock and suspend operations

■ Clock-controlled and registered address, data and control signals

■ Registered output for pipelined applications

■ Three separate chip enables allow wide range of options for CE control, address pipelining

■ Internally self-timed write cycle

■ Selectable BURST mode (Linear or Interleaved)

■ SLEEP mode (ZZ pin) provided

■ Available in 100 pin LQFP package