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A67P8318E-4.2F規(guī)格書詳情
General Description
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.
The A67P8318, A67P7336 SRAMs integrate a 256K X 18, 128K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation.
Features
■ Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz)
■ Zero Bus Latency between READ and WRITE cycles allows 100 bus utilization
■ Signal +2.5V ± 5 power supply
■ Individual Byte Write control capability
■ Clock enable ( CEN) pin to enable clock and suspend operations
■ Clock-controlled and registered address, data and control signals
■ Registered output for pipelined applications
■ Three separate chip enables allow wide range of options for CE control, address pipelining
■ Internally self-timed write cycle
■ Selectable BURST mode (Linear or Interleaved)
■ SLEEP mode (ZZ pin) provided
■ Available in 100 pin LQFP package
產(chǎn)品屬性
- 型號：
A67P8318E-4.2F
- 制造商：
AMICC
- 制造商全稱：
AMIC Technology
- 功能描述：
256K X 18, 128K X 36 LVTTL, Pipelined ZeBL SRAM
