ACS175DMSR-03中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Radiation Hardened Quad D-Type Flip Flop with Reset

The Radiation Hardened ACS175MS is a Quad D-Type Flip-Flop with Reset. Information at the D input is

transferred to the Q and Q outputs on the positive-going transition of the clock. All four flip-flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a LOW level independent of the clock. All inputs are buffered and the outputs are designed for balanced propagation delay and transition times.

Features

? QML Qualified Per MIL-PRF-38535 Requirements

? 1.25 Micron Radiation Hardened SOS CMOS

? Radiation Environment

- Latch-Up Free Under Any Conditions

- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si)

- SEU Immunity . . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day

- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm2)

? Input Logic Levels. . . . VIL= (0.3)(VCC), VIH= (0.7)(VCC)

? Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)

? Quiescent Supply Current . . . . . . . . . . . . . . . 10μA (Max)

? Propagation Delay . . . . . . . . . . . . . . . . . . . . . .22ns (Max)

Applications

? High Speed Control Circuits

? Sensor Monitoring

? Low Power Designs