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ACTS112D中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書

ACTS112D
廠商型號

ACTS112D

功能描述

Radiation Hardened Dual J-K Flip-Flop

文件大小

237.06 Kbytes

頁面數(shù)量

3

生產(chǎn)廠商 Intersil Corporation
企業(yè)簡稱

Intersil

中文名稱

Intersil Corporation官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-1-30 11:12:00

ACTS112D規(guī)格書詳情

Description

The Intersil ACTS112MS is a Radiation Hardened Dual J-K Flip-Flop with Set and Reset. The output change states on the negative transition of the clock (CP1N or CP2N).

The ACTS112MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.

The ACTS112MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix).

Features

? Devices QML Qualified in Accordance with MIL-PRF-38535

? Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96714 and Intersil’s QM Plan

? 1.25 Micron Radiation Hardened SOS CMOS

? Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

? Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ)

? SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg

? Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse

? Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse

? Latch-Up Free Under Any Conditions

? Military Temperature Range . . . . . . . . . . . . . . . . . . -55°C to +125°C

? Significant Power Reduction Compared to ALSTTL Logic

? DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

? Input Logic Levels

??? - VIL = 0.8V Max

??? - VIH = VCC/2 Min

? Input Current ≤ 1μA at VOL, VOH

? Fast Propagation Delay . . . . . . . . . . . . . . . . 26ns (Max), 16ns (Typ)

產(chǎn)品屬性

  • 型號:

    ACTS112D

  • 制造商:

    INTERSIL

  • 制造商全稱:

    Intersil Corporation

  • 功能描述:

    Radiation Hardened Dual J-K Flip-Flop

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