AD1893JST集成電路（IC）的音頻專用規(guī)格書PDF中文資料

AD1893JST屬于集成電路（IC）的音頻專用。由亞德諾半導體技術有限公司制造生產(chǎn)的AD1893JST音頻專用音頻專用的半導體器件專為音頻信號的濾波、驅動、放大、轉換和接口而設計。特征包括功能、應用、通道數(shù)、接口、電壓和規(guī)格。應用包括音頻系統(tǒng)、汽車音頻、消費類音頻、樂器、專業(yè)音頻、通信系統(tǒng)、電信系統(tǒng)、數(shù)字音頻、驅動器、前置放大器、信號混合、信號處理、語音觸發(fā)器解決方案和 10 Base-T。

PRODUCT OVERVIEW

The AD1893 SamplePort is a fully digital, stereo Asynchronous Sample Rate Converter (ASRC) that solves sample rate interfacing and compatibility problems in digital audio equipment. Conceptually, this converter interpolates the input data up to a very high internal sample rate with a time resolution of 300 ps, then decimates down to the desired output sample rate. The AD1893 is intended for 16-bit low cost, non-varispeed applications where low voltage, low power (i.e., battery-powered) operation is required. Refer to the AD1890/AD1891 data sheet for other products in the SamplePort family. This device is asynchronous because the frequency and phase relationships between the input and output sample clocks (both are inputs to the AD1893 ASRC) are arbitrary and need not be related by a simple integer ratio. There is no need to explicitly select or program the input and output sample clock frequencies, as the AD1893 automatically senses the relationship between the two clocks. The input and output sample clock frequencies can nominally range from 8 kHz to 56 kHz, and the ratio between them can vary from approximately 1:2 to 2:1.

The AD1893 uses multirate digital signal processing techniques to construct an output sample stream from the input sample stream. The input word width is 4 to 16 bits for the AD1893. Shorter input words are automatically zero-filled in the LSBs. The output word width is 24 bits. The user can receive as many of the output bits as desired. Internal arithmetic is performed with 22-bit coefficients and 27-bit accumulation. The digital samples are processed with unity gain.

FEATURES

Low Cost

LQFP and PDIP Packages

3 V Supply Performance Specified—Very Low Power

Automatically Senses Sample Frequencies—No Programming Required

Rejects Sample Clock Jitter

Accommodates Dynamically Changing Asynchronous Sample Clocks

8 kHz to 56 kHz Sample Clock Frequency Range

Approximately 1:2 to 2:1 Ratio Between Sample Clocks

–96 dB THD+N at 1 kHz

96 dB Dynamic Range

Optimal Clock Tracking Control—Slow/Fast Settling Modes

Linear Phase in All Modes

Automatic Output Mute

Flexible Four-Wire Serial Interfaces with Right-Justified

Mode

Power-Down Mode

On-Chip Oscillator

APPLICATIONS

Consumer CD-R, DAT, DCC, MD and 8 mm Video Tape

Recorders Including Portables

Digital Audio Communication/Network Systems

Computer Multimedia Systems