AD5300集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書PDF中文資料

AD5300屬于集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD5300數(shù)模轉(zhuǎn)換器（DAC）數(shù)模轉(zhuǎn)換器（DAC、D/A、D2A 或 D 轉(zhuǎn) A）可將數(shù)字信號轉(zhuǎn)換為緩沖或無緩沖的模擬電壓或電流。DAC 架構(gòu)是否適合特定應(yīng)用，要取決于分辨率和采樣頻率。DAC 通常用于音樂播放器，將數(shù)字數(shù)據(jù)流轉(zhuǎn)換為模擬音頻流。它們還用于電視和手機，將數(shù)字視頻數(shù)據(jù)轉(zhuǎn)換為模擬視頻信號，再連接到屏幕驅(qū)動器，以顯示單色或彩色圖像。

GENERAL DESCRIPTION

The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12- bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 115 μA at 3 V and feature a power-down mode that further reduces the current to 80 nA. The devices incorporate an on-chip output buffer that can drive the output to both supply rails, but the AD5330, AD5340, and AD5341 allow a choice of buffered or unbuffered reference input.

FEATURES

AD5330: single 8-bit DAC in 20-lead TSSOP

AD5331: single 10-bit DAC in 20-lead TSSOP

AD5340: single 12-bit DAC in 24-lead TSSOP

AD5341: single 12-bit DAC in 20-lead TSSOP

Low power operation: 115 μA @ 3 V, 140 μA @ 5 V

Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin

2.5 V to 5.5 V power supply

Double-buffered input logic

Guaranteed monotonic by design over all codes

Buffered/unbuffered reference input options

Output range: 0 V to VREF or 0 V to 2 × VREF

Power-on reset to 0 V

Simultaneous update of DAC outputs via LDAC pin

Asynchronous CLR facility

Low power parallel data interface

On-chip rail-to-rail output buffer amplifiers

Temperature range: ?40°C to +105°C

APPLICATIONS

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

Industrial process control