AD5621集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書PDF中文資料

AD5621屬于集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導體技術(shù)有限公司制造生產(chǎn)的AD5621數(shù)模轉(zhuǎn)換器（DAC）數(shù)模轉(zhuǎn)換器（DAC、D/A、D2A 或 D 轉(zhuǎn) A）可將數(shù)字信號轉(zhuǎn)換為緩沖或無緩沖的模擬電壓或電流。DAC 架構(gòu)是否適合特定應(yīng)用，要取決于分辨率和采樣頻率。DAC 通常用于音樂播放器，將數(shù)字數(shù)據(jù)流轉(zhuǎn)換為模擬音頻流。它們還用于電視和手機，將數(shù)字視頻數(shù)據(jù)轉(zhuǎn)換為模擬視頻信號，再連接到屏幕驅(qū)動器，以顯示單色或彩色圖像。

GENERAL DESCRIPTION

The AD5601/AD5611/AD5621, members of the nanoDAC? family, are single, 8-/10-/12-bit, buffered voltage output DACs that operate from a single 2.7 V to 5.5 V supply, consuming typically 75 μA at 5 V. The parts come in tiny LFCSP and SC70 packages. Their on-chip precision output amplifier allows rail to-rail output swing to be achieved. The AD5601/AD5611/ AD5621 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI, QSPI?, MICROWIRE?, and DSP interface standards.

FEATURES

6-lead SC70 and LFCSP packages

Micropower operation: 100 μA maximum at 5 V

Power-down typically to 0.2 μA at 3 V

2.7 V to 5.5 V power supply

Guaranteed monotonic by design

Power-on reset to 0 V with brownout detection

3 power-down functions

Low power serial interface with Schmitt-triggered inputs

On-chip output buffer amplifier, rail-to-rail operation

SYNC interrupt facility

Minimized zero-code error

AD5601 buffered 8-bit DAC

B version: ±0.5 LSB INL

AD5611 buffered 10-bit DAC

B version: ±0.5 LSB INL

A version: ±4 LSB INL

AD5621 buffered 12-bit DAC

B version: ±1 LSB INL

A version: ±6 LSB INL

APPLICATIONS

Voltage level setting

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators