GENERAL DESCRIPTION

The AD632 is an internally trimmed monolithic four-quadrant multiplier/divider. The AD632B has a maximum multiplying error of ±0.5 without external trims.

FEATURES

Pretrimmed to ±0.5 maximum 4-quadrant error

All inputs (X, Y, and Z) differential, high impedance for

[(X1 ? X2)(Y1 ? Y2)/10] + Z2 transfer function

Scale-factor adjustable to provide up to ×10 gain

Low noise design: 90 mV rms, 10 Hz to 10 kHz

Low cost, monolithic construction

Excellent long-term stability

APPLICATIONS

High quality analog signal processing

Differential ratio and percentage computations

Algebraic and trigonometric function synthesis

Accurate voltage controlled oscillators and filters

AD632SD屬于集成電路（IC） > 模擬乘法器、除法器。亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD632SD模擬乘法器、除法器模擬乘法器獲取兩個或更多模擬信號，并產(chǎn)生這些信號的乘積或乘積之和的輸出。此類電路可用于實現(xiàn)相關(guān)計算功能，例如計算平方（對兩個輸入都施加相同的信號）和平方根。應(yīng)用可能包括可變增益放大器、環(huán)形調(diào)制器、乘積檢測器、混頻器、增益控制、真 RMS 轉(zhuǎn)換器和脈沖幅度調(diào)制器 (PAM)。