AD633集成電路（IC）的模擬乘法器、除法器規(guī)格書PDF中文資料

AD633屬于集成電路（IC）的模擬乘法器、除法器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD633模擬乘法器、除法器模擬乘法器獲取兩個或更多模擬信號，并產(chǎn)生這些信號的乘積或乘積之和的輸出。此類電路可用于實現(xiàn)相關(guān)計算功能，例如計算平方（對兩個輸入都施加相同的信號）和平方根。應(yīng)用可能包括可變增益放大器、環(huán)形調(diào)制器、乘積檢測器、混頻器、增益控制、真 RMS 轉(zhuǎn)換器和脈沖幅度調(diào)制器 (PAM)。

GENERAL DESCRIPTION

The AD633 is a functionally complete, four-quadrant, analog multiplier. It includes high impedance, differential X and Y inputs, and a high impedance summing input (Z). The low impedance output voltage is a nominal 10 V full scale provided by a buried Zener. The AD633 is the first product to offer these features in modestly priced 8-lead PDIP and SOIC packages.

FEATURES

4-quadrant multiplication

Low cost, 8-lead SOIC and PDIP packages

Complete—no external components required

Laser-trimmed accuracy and stability

Total error within 2 of full scale

Differential high impedance X and Y inputs

High impedance unity-gain summing input

Laser-trimmed 10 V scaling reference

APPLICATIONS

Multiplication, division, squaring

Modulation/demodulation, phase detection

Voltage-controlled amplifiers/attenuators/filters