AD6652RF/IF射頻/中頻RFID的RFIC模塊規(guī)格書(shū)PDF中文資料

AD6652屬于RF/IF射頻/中頻RFID的RFIC模塊。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD6652RF 其它 IC 和模塊RF 其它 IC 和模塊產(chǎn)品系列包含各種獨(dú)特、專(zhuān)門(mén)或特定用途的產(chǎn)品，可與 RF、IF 和微波無(wú)線(xiàn)電應(yīng)用結(jié)合使用。示例包括 AM/FM 調(diào)諧器和接收器、偏置網(wǎng)絡(luò)、基帶處理器、計(jì)數(shù)器、數(shù)字可調(diào)電容器、下變頻器、倍頻器、移相器、前置分頻器、端接器、上變頻器、VCO 等。

PRODUCT DESCRIPTION

The AD6652 is a mixed-signal IF to baseband receiver consisting of dual 12-bit 65 MSPS ADCs and a wideband multimode digital downconverter (DDC). The AD6652 is designed to support communications applications where low cost, small size, and versatility are desired. The AD6652 is also suitable for other applications in imaging, medical ultrasound, instrumentation, and test equipment.

FEATURES

SNR = 90 dB in 150 kHz bandwidth (to Nyquist @ 61.44 MSPS)

Worst harmonic = 83 dBc (to Nyquist @ 61.44 MSPS)

Integrated dual-channel ADC:

Sample rates up to 65 MSPS

IF sampling frequencies to 200 MHz

Internal ADC voltage reference

Integrated ADC sample-and-hold inputs

Flexible analog input range (1 V to 2 V p-p)

Differential analog inputs

ADC clock duty cycle stabilizer

85 dB channel isolation/crosstalk

Integrated wideband digital downconverter (DDC):

Crossbar switched DDC inputs

Digital resampling for noninteger decimation

Programmable decimating FIR filters

Flexible control for multicarrier and phased array

Dual AGC stages for output level control

Dual 16-bit parallel or 8-bit link output ports

User-configurable built-in self-test (BIST) capability

Energy-saving power-down modes

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers:

GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE,

IS95, IS136, CDMA2000, IMT-2000

I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Broadband data applications

Instrumentation and test equipment