AD7262BCPZ-5-RL7集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD7262BCPZ-5-RL7屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD7262BCPZ-5-RL7模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風(fēng)采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

GENERAL DESCRIPTION

The AD7262/AD7262-5 are dual, 12-bit, high speed, low power, successive approximation ADCs that operate from a single 5 V power supply. The AD7262 features throughput rates of up to 1 MSPS per on-chip ADC.The AD7262-5 features throughput rates of up to 500 kSPS. Two complete ADC functions allow simultaneous sampling and conversion of two channels. Each ADC is preceded by a true differential analog input with a PGA. There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, and ×128.

FEATURES

Dual simultaneous sampling 12-bit, 2-channel analog-to-digital converter (ADC)

True differential analog inputs

Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16,

×24, ×32, ×48, ×64, ×96, ×128

Throughput rate per ADC

1 MSPS for AD7262

500 kSPS for AD7262-5

Analog input impedance: >1 GΩ

Wide input bandwidth

?3 dB bandwidth: 1.7 MHz at gain = 2

4 on-chip comparators

SNR: 73 dB typical at gain = 2, 66 dB typical at gain = 32

Device offset calibration, system gain calibration

On-chip reference: 2.5 V

?40°C to +105°C operation

High speed serial interface

SPI/QSPI?/MICROWIRE/DSP compatible

48-lead LFCSP and LQFP