AD734SQ集成電路（IC）的模擬乘法器、除法器規(guī)格書PDF中文資料

AD734SQ屬于集成電路（IC）的模擬乘法器、除法器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD734SQ模擬乘法器、除法器模擬乘法器獲取兩個(gè)或更多模擬信號(hào)，并產(chǎn)生這些信號(hào)的乘積或乘積之和的輸出。此類電路可用于實(shí)現(xiàn)相關(guān)計(jì)算功能，例如計(jì)算平方（對(duì)兩個(gè)輸入都施加相同的信號(hào)）和平方根。應(yīng)用可能包括可變?cè)鲆娣糯笃鳌h(huán)形調(diào)制器、乘積檢測(cè)器、混頻器、增益控制、真 RMS 轉(zhuǎn)換器和脈沖幅度調(diào)制器 (PAM)。

GENERAL DESCRIPTION

The AD734 is an accurate high speed, four-quadrant analog multiplier that is pin compatible with the industry-standard AD534 and provides the transfer function W = XY/U. The AD734 provides a low impedance voltage output with a full power (20 V p-p) bandwidth of 10 MHz. Total static error (scaling, offsets, and nonlinearities combined) is 0.1 of full scale. Distortion is typically less than ?80 dBc and guaranteed. The low capacitance X, Y, and Z inputs are fully differential. In most applications, no external components are required to define the function.

The internal scaling (denominator) voltage, U, is 10 V, derived from a buried-Zener voltage reference. A new feature provides the option of substituting an external denominator voltage, allowing the use of the AD734 as a two-quadrant divider with a 1000:1 denominator range and a signal bandwidth that remains 10 MHz to a gain of 20 dB, 2 MHz at a gain of 40 dB, and 200 kHz at a gain of 60 dB, for a gain-bandwidth product of 200 MHz.

FEATURES

High accuracy

0.1 typical error

High speed

10 MHz full power bandwidth

450 V/μs slew rate

200 ns settling to 0.1 at full power

Low distortion

?80 dBc from any input

Third-order IMD typically ?75 dBc at 10 MHz

Low noise

94 dB SNR, 10 Hz to 20 kHz

70 dB SNR, 10 Hz to 10 MHz

Direct division mode

2 MHz BW at gain of 100