AD7384-4BCPZ-RL中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The 16-bit AD7383-4 and 14-bit AD7384-4 are pin-compatible,

quad, simultaneous sampling, high speed, successive approximation

register (SAR), analog-to-digital converters (ADCs) operating

from a 3.0 V to 3.3 V power supply with throughput rates up to

4 MSPS. The analog input type is a pseudo differential and is

sampled and converted on the falling edge of CS.

The AD7383-4/AD7384-4 have on-chip oversampling blocks to

improve dynamic range and reduce noise at lower bandwidths. The

oversampling boosts up to two bits of added resolution. A buffered

internal 2.5 V reference is included. Alternatively, an external reference

up to 3.3 V can be used.

The conversion process and data acquisition use standard control

inputs allowing easy interfacing to microprocessors or digital signal

processors (DSPs). The conversion result can clock out simultaneously

via 4-wire mode for faster throughput or via 1-wire serial

mode when slower throughput is allowed. The devices are compatible

with 1.8 V, 2.5 V, and 3.3 V interfaces using the separate logic supply.

FEATURES

? 16-bit and 14-bit ADC family

? Quad simultaneous sampling

? Pseudo differential analog inputs

? High throughput rate: 4 MSPS

? SNR: 86.7 dB (typical) at VREF = 3.3 V (AD7383-4)

? On-chip oversampling function

? SNR: 91 dB (typical) with OSR = 8×, RES = 1

? 2-bit resolution boost

? Out of range indicator (ALERT)

? INL: 3.8 LSBs (maximum)

? High speed serial interface

? Temperature range: ?40°C to +125°C

? 24-lead, 4 mm × 4 mm LFCSP

APPLICATIONS

? Motor control position feedback

? Motor control current sense

? Data acquisition systems

? Erbium-doped fiber amplifier (EDFA) applications

? Inphase and quadrature demodulation

PRODUCT HIGHLIGHTS

1. Quad simultaneous sampling and conversion.

2. Pin-compatible product family.

3. High 4 MSPS throughput rate.

4. Space-saving 4 mm × 4 mm LFCSP.

5. Integrated oversampling block to increase dynamic range, reduce

noise, and reduce SCLK speed requirements.

6. Pseudo differential analog inputs.

7. Small sampling capacitor reduces amplifier drive burden.