AD805開發(fā)板套件編程器的評估板-運(yùn)算放大器規(guī)格書PDF中文資料

AD805屬于開發(fā)板套件編程器的評估板-運(yùn)算放大器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD805評估板 - 運(yùn)算放大器運(yùn)算放大器評估板是裝有元器件的電路，用于提供特定集成電路或器件的工作實(shí)例。該產(chǎn)品族中的電路板提供了運(yùn)算放大器實(shí)例。每個(gè) IC 的通道類型有單通道、雙通道、三通道、四通道和八通道，放大器類型包括音頻、自動(dòng)歸零、緩沖器、斬波器、電流反饋、電流檢測、差動(dòng)、差分、四通道、儀表、隔離、J-FET、限幅、對數(shù)、功率、可編程增益、采樣保持、跨阻、可變增益、視頻、電壓反饋和零漂移。

PRODUCT DESCRIPTION

The AD805 is a data retiming phase-locked loop designed for use with a Voltage-Controlled Crystal Oscillator (VCXO) to perform clock recovery and data retiming on Nonreturn to Zero (NRZ) data. The circuit provides clock recovery and data retiming on standard telecommunications STS-3 or STM-1 data (155.52 Mbps). A Vectron C0-434Y Series VCXO circuit is used with the AD805 for specification purposes. Similar circuit performance can be obtained using other commercially available VCXO circuits. The AD805-VCXO circuit used for clock recovery and data retiming can also be used for large factor frequency multiplication.

FEATURES

155 Mbps Clock Recovery and Data Retiming

Permits CCITT G.958 Type A Jitter Tolerance

Permits CCITT G.958 Type B Jitter Transfer

Random Jitter: 0.68 rms

Pattern Jitter: Virtually Eliminated

Jitter Peaking: Fundamentally None

Acquisition: 30 Bit Periods

Accepts NRZ Data without Preamble

Single Supply Operation: –5.2 V or +5 V

10 KH ECL Compatible