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AD805BN中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

AD805BN
廠商型號(hào)

AD805BN

功能描述

DATA RETIMING PHASE LOCKED LOOP

文件大小

318.83 Kbytes

頁(yè)面數(shù)量

12 頁(yè)

生產(chǎn)廠商 Analog Devices
企業(yè)簡(jiǎn)稱

AD亞德諾

中文名稱

亞德諾半導(dǎo)體技術(shù)有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-14 12:36:00

AD805BN規(guī)格書(shū)詳情

PRODUCT DESCRIPTION

The AD805 is a data retiming phase-locked loop designed for use with a Voltage-Controlled Crystal Oscillator (VCXO) to perform clock recovery and data retiming on Nonreturn to Zero (NRZ) data. The circuit provides clock recovery and data retiming on standard telecommunications STS-3 or STM-1 data (155.52 Mbps). A Vectron C0-434Y Series VCXO circuit is used with the AD805 for specification purposes. Similar circuit performance can be obtained using other commercially available VCXO circuits. The AD805-VCXO circuit used for clock recovery and data retiming can also be used for large factor frequency multiplication.

FEATURES

155 Mbps Clock Recovery and Data Retiming

Permits CCITT G.958 Type A Jitter Tolerance

Permits CCITT G.958 Type B Jitter Transfer

Random Jitter: 0.68 rms

Pattern Jitter: Virtually Eliminated

Jitter Peaking: Fundamentally None

Acquisition: 30 Bit Periods

Accepts NRZ Data without Preamble

Single Supply Operation: –5.2 V or +5 V

10 KH ECL Compatible

產(chǎn)品屬性

  • 型號(hào):

    AD805BN

  • 制造商:

    Rochester Electronics LLC

  • 功能描述:

    - Bulk

  • 制造商:

    Analog Devices

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N/A
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