AD8152_V01中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書

FEATURES

Low cost

Low power: 2.5 V (outputs disabled)

34 × 34, fully differential, nonblocking array

3.2 Gbps per port NRZ data rate

Wide power supply range: 2.5 V to 3.3 V

LVTTL or LVCMOS level control inputs at

2.5 V to 3.3 V

Low channel jitter: 45 ps p-p

Drives a backplane directly

Programmable output swing

100 mV to 1600 mV p-p differential

50 Ω on-chip input/output termination

User controlled voltage at the load

Minimizes power dissipation

Dual rank latches

Available in 256-ball BGA_ED package

APPLICATIONS

Fiber optic network switching

High speed serial backplane routing to OC-48 with FEC

Gigabit ethernet

Digital video (HDTV)

Data storage networks