AD8152JBP集成電路（IC）的信號(hào)開關(guān)多路復(fù)用器解碼器規(guī)格書PDF中文資料

AD8152JBP屬于集成電路（IC）的信號(hào)開關(guān)多路復(fù)用器解碼器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD8152JBP信號(hào)開關(guān)，多路復(fù)用器，解碼器邏輯型信號(hào)開關(guān)、多路復(fù)用器和編碼器 IC 可用于對(duì)以數(shù)字格式表示數(shù)據(jù)的電信號(hào)進(jìn)行路由和選擇。這些器件與設(shè)計(jì)用于模擬信號(hào)的類似產(chǎn)品有所不同，它們保留的信息表示為兩個(gè)電狀態(tài)之一，而不是兩個(gè)外部界限內(nèi)的無窮變化量。

GENERAL DESCRIPTION

AD8152 is a member of the Xstream line of products and is a breakthrough in digital switching, offering a large switch array (34 × 34) on very little power, typically 2.0 W. Additionally, it operates at data rates up to 3.2 Gbps per port, making it suitable for Sonet/SDH OC-48 with Forward Error Correction (FEC).

The AD8152’s useful supply voltage range allows the user to operate at LVPECL/CML data levels down to 2.5 V. The control interface is LVTTL or LVCMOS compatible on 2.5 V to 3.3 V.

The AD8152’s fully differential signal path reduces jitter and crosstalk while allowing the use of smaller single-ended voltage swings. It is offered in a 256-ball SBGA package that operates over the industrial temperature range of 0°C to 85°C.

FEATURES

Low Cost

Low Power

2.0 W @ 2.5 V (Outputs Enabled)

<100 mW @ 2.5 V (Outputs Disabled)

34 x 34, Fully Differential, Nonblocking Array

3.2 Gbps per Port NRZ Data Rate

Wide Power Supply Range: 2.5 V to 3.3 V

LVTTL or LVCMOS Level Control Inputs:

@ 2.5 V to 3.3 V

Low Jitter: 45 ps

Drives a Backplane Directly

Programmable Output Swing

100 mV to 1.6 V Differential

50Ω On-Chip I/O Termination

User Controlled Voltage at the Load

Minimizes Power Dissipation

Dual Rank Latches

Available in 256-Ball Grid Array

APPLICATIONS

Fiber Optic Network Switching

High Speed Serial Backplane Routing to OC-48 with FEC

Gigabit Ethernet

Digital Video (HDTV)

Data Storage Networks