AD9148集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書(shū)PDF中文資料

AD9148屬于集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9148數(shù)模轉(zhuǎn)換器（DAC）數(shù)模轉(zhuǎn)換器（DAC、D/A、D2A 或 D 轉(zhuǎn) A）可將數(shù)字信號(hào)轉(zhuǎn)換為緩沖或無(wú)緩沖的模擬電壓或電流。DAC 架構(gòu)是否適合特定應(yīng)用，要取決于分辨率和采樣頻率。DAC 通常用于音樂(lè)播放器，將數(shù)字?jǐn)?shù)據(jù)流轉(zhuǎn)換為模擬音頻流。它們還用于電視和手機(jī)，將數(shù)字視頻數(shù)據(jù)轉(zhuǎn)換為模擬視頻信號(hào)，再連接到屏幕驅(qū)動(dòng)器，以顯示單色或彩色圖像。

GENERAL DESCRIPTION

The AD9148 is a quad, 16-bit, high dynamic range, digital-toanalog converter (DAC) that provides a sample rate of 1000 MSPS. This device includes features optimized for direct conversion transmit applications, including gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators such as the ADL5371/ADL5372/ADL5373/ADL5374/ADL5375.

FEATURES

Single-carrier W-CDMA ACLR = 80 dBc at 150 MHz IF

Channel-to-channel isolation > 90 dB

Analog output

Adjustable 8.7 mA to 31.7 mA

RL = 25 Ω to 50 Ω

Novel 2×, 4×, and 8× interpolator eases data interface

On-chip fine complex NCO allows carrier placement anywhere in DAC bandwidth

High performance, low noise PLL clock multiplier

Multiple chip synchronization interface

Programmable digital inverse sinc filter

Auxiliary DACs allow for offset control

Gain DACs allow for I and Q gain matching

Programmable I and Q phase compensation

Digital gain control

Flexible LVDS digital I/F supports 32- or 16-bit bus width

196-ball CSP_BGA, 12 mm × 12 mm

APPLICATIONS

Wireless infrastructure

LTE, TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM

MIMO/transmit diversity

Digital high or low IF synthesis