AD9172開發(fā)板套件編程器的評估板-數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書PDF中文資料

AD9172屬于開發(fā)板套件編程器的評估板-數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9172評估板 - 數(shù)模轉(zhuǎn)換器（DAC）該系列產(chǎn)品提供了一種方便的方法，在經(jīng)過驗證的設(shè)計環(huán)境中對用于將數(shù)字?jǐn)?shù)據(jù)轉(zhuǎn)換為模擬格式的器件進(jìn)行性能或特性評估。重點(diǎn)器件涵蓋范圍從以適合學(xué)生或愛好者使用的方式實現(xiàn)的適度功能器件，到適合電信基礎(chǔ)設(shè)施應(yīng)用的高級器件。

FEATURES

? Supports multiband wireless applications

? 3 bypassable, complex data input channels per RF DAC

? 1.54 GSPS maximum complex input data rate per input channel

? 1 independent NCO per input channel

? Proprietary, low spurious and distortion design

? 2-tone intermodulation distortion (IMD) = ?83 dBc at 1.8 GHz,

?7 dBFS/tone RF output

? Spurious free dynamic range (SFDR)

?7 dBFS RF output

? Flexible 8-lane, 15.4 Gbps JESD204B interface

? Supports single-band and multiband use cases

? Supports 12-bit high density mode for increased data throughput

? Multiple chip synchronization

? Supports JESD204B Subclass 1

? Selectable interpolation filter for a complete set of input data

rates

? 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation

? 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation

? Final 48-bit NCO that operates at the DAC rate to support

frequency synthesis up to 6 GHz

? Transmit enable function allows extra power saving and downstream

circuitry protection

? High performance, low noise PLL clock multiplier

? Supports 12.6 GSPS DAC update rate

? Observation ADC clock driver with selectable divide ratios

? Low power

? 2.55 W at 12 GSPS, dual channel mode

? 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal

lid, 0.80 mm pitch

APPLICATIONS

? Wireless communications infrastructure

? Multiband base station radios

? Microwave/E-band backhaul systems

? Instrumentation, automatic test equipment (ATE)

? Radars and jammers