AD9174_V02中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

FEATURES

Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC

3.08 GSPS maximum complex input data rate per input

channel

1 independent NCO per input channel

Proprietary, low spurious and distortion design

2-tone IMD3 = ?83 dBc at 1.84 GHz, ?7 dBFS/tone RF output SFDR

Flexible 8-lane, 15.4 Gbps JESD204B interface

Supports single-band and multiband use cases

Supports 12-bit high density mode for increased data

throughput

Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input

data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel

interpolation

1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation

Final 48-bit NCO that operates at the DAC rate to support

frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and

downstream circuitry protection

High performance, low noise PLL clock multiplier

Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power

2.54 W with 2 DACs at 12 GSPS, DAC PLL on

10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

APPLICATIONS

Wireless communications infrastructure Multiband base station radios

Microwave/E-band backhaul systems

Instrumentation, automatic test equipment (ATE)

Radars and jammers