AD9250集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD9250屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導體技術有限公司制造生產(chǎn)的AD9250模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

GENERAL DESCRIPTION

The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.

FEATURES

JESD204B Subclass 0 or Subclass 1 coded serial digital outputs

Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and

250 MSPS

Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz

AIN and 250 MSPS

Total power consumption: 711 mW at 250 MSPS

1.8 V supply voltages

Integer 1-to-8 input clock divider

Sample rates of up to 250 MSPS

IF sampling frequencies of up to 400 MHz

Internal analog-to-digital converter (ADC) voltage reference

Flexible analog input range

1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)

ADC clock duty cycle stabilizer (DCS)

95 dB channel isolation/crosstalk

Serial port control

Energy saving power-down modes

APPLICATIONS

Diversity radio systems

Multimode digital receivers (3G)

TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE

DOCSIS 3.0 CMTS upstream receive paths

HFC digital reverse path receivers

I/Q demodulation systems

Smart antenna systems

Electronic test and measurement equipment

Radar receivers

COMSEC radio architectures

IED detection/jamming systems

General-purpose software radios

Broadband data applications