AD9251BCPZRL7-80集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD9251BCPZRL7-80屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導體技術(shù)有限公司制造生產(chǎn)的AD9251BCPZRL7-80模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

GENERAL DESCRIPTION

The AD9251 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-andhold circuit and on-chip voltage reference.

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply

SNR

74.3 dBFS at 9.7 MHz input

71.5 dBFS at 200 MHz input

SFDR

93 dBc at 9.7 MHz input

80 dBc at 200 MHz input

Low power

33 mW per channel at 20 MSPS

73 mW per channel at 80 MSPS

Differential input with 700 MHz bandwidth

On-chip voltage reference and sample-and-hold circuit

2 V p-p differential analog input

DNL = ±0.45 LSB

Serial port control options

Offset binary, gray code, or twos complement data format

Optional clock duty cycle stabilizer

Integer 1-to-8 input clock divider

Data output multiplex option

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out with programmable clock and data alignment

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

Battery-powered instruments

Hand held scope meters

Portable medical imaging

Ultrasound

Radar/LIDAR