AD9433BSVZ-125集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD9433BSVZ-125屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9433BSVZ-125模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風(fēng)采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

GENERAL INTRODUCTION

The AD9433 is a 12-bit, monolithic sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit and is designed for ease of use. The product operates up to a 125 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband and high IF carrier systems.

FEATURES

IF sampling up to 350 MHz

SNR: 67.5 dB, fIN up to Nyquist at 105 MSPS

SFDR: 83 dBc, fIN = 70 MHz at 105 MSPS

SFDR: 72 dBc, fIN = 150 MHz at 105 MSPS

2 V p-p analog input range

On-chip clock duty cycle stabilization

On-chip reference and track-and-hold

SFDR optimization circuit

Excellent linearity

DNL: ±0.25 LSB (typical)

INL: ±0.5 LSB (typical)

750 MHz full power analog bandwidth

Power dissipation: 1.35 W (typical) at 125 MSPS

Twos complement or offset binary data format

5.0 V analog supply operation

2.5 V to 3.3 V TTL/CMOS outputs

APPLICATIONS

Cellular infrastructure communication systems

3G single- and multicarrier receivers

IF sampling schemes

Wideband carrier frequency systems

Point-to-point radios

LMDS, wireless broadband

MMDS base station units

Cable reverse path

Communications test equipment

Radar and satellite ground systems