AD9500BP中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書

GENERAL DESCRIPTION

The AD9500 is a digitally programmable delay generator, which provides programmed delays, selected through an 8-bit digital code, in resolutions as small as 10 ps. The AD9500 is constructed in a high performance bipolar process, designed to provide high speed operation for both digital and analog circuits.

The AD9500 employs differential TRIGGER and RESET inputs which are designed primarily for ECL signal levels but function with analog and TTL input levels. An onboard ECL reference midpoint allows both of the inputs to be driven by either single ended or differential ECL circuits. The AD9500 output is a complementary ECL stage, which also provides a QR parallel output circuit to facilitate reset timing implementations.

The digital control data is passed to the AD9500 through a transparent latch controlled by the LATCH ENABLE signal. In the transparent mode, the internal DAC of the AD9500 will attempt to follow changes at the inputs. The LATCH ENABLE is otherwise used to strobe the digital data into the AD9500 latches.

FEATURES

10 ps Delay Resolution

2.5 ns to 10 ms Full-Scale Range

Fully Differential Inputs

Separate Trigger and Reset Inputs

Low Power Dissipation—310 mW

MIL-STD-883 Compliant Versions Available

APPLICATIONS

ATE

Pulse Deskewing

Arbitrary Waveform Generators

High Stability Timing Source

Multiple Phase Clock Generators