AD9512集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器規(guī)格書(shū)PDF中文資料

AD9512屬于集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9512時(shí)鐘緩沖器，驅(qū)動(dòng)器時(shí)鐘緩沖器和驅(qū)動(dòng)器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號(hào)在系統(tǒng)中傳輸，常用作頻率/時(shí)間參考信號(hào)，以同步系統(tǒng)內(nèi)的活動(dòng)。盡管這些器件最常用到的功能就是緩沖（即，為使信號(hào)不受驅(qū)動(dòng)負(fù)載的影響而從某個(gè)信號(hào)源復(fù)制信號(hào)），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號(hào)路徑、按某個(gè)整數(shù)值分割信號(hào)頻率，或進(jìn)行所用電信號(hào)格式轉(zhuǎn)換。

GENERAL DESCRIPTION

The AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part.

There are five independent clock outputs. Three outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels.

FEATURES

Two 1.6 GHz, differential clock inputs

5 programmable dividers, 1 to 32, all integers

Phase select for output-to-output coarse delay adjust

3 independent 1.2 GHz LVPECL outputs

Additive output jitter 225 fs rms

2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs

Additive output jitter 275 fs rms

Fine delay adjust on 1 LVDS/CMOS output

Serial control port

Space-saving 48-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure