AD9520-2/PCBZ開發(fā)板套件編程器的評估演示板及套件規(guī)格書PDF中文資料

AD9520-2/PCBZ屬于開發(fā)板套件編程器的評估演示板及套件。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9520-2/PCBZ評估和演示板及套件該系列產(chǎn)品提供了一種方便的方法，在經(jīng)過驗證的實(shí)施環(huán)境中評估某些重點(diǎn)器件的性能或特性。評估方法通常有完善的文檔說明，并且視乎具體情況由評估軟件提供支持。產(chǎn)品通常由印刷電路板組成，板上已裝有重點(diǎn)器件以及必要或有用的支持元器件，另外也可能包括其他組件，例如電纜或電源。對于數(shù)量特別多或類別獨(dú)特的器件類別(如 ADC、DAC 和開關(guān)模式電源)，評估平臺可組合為一個單獨(dú)的產(chǎn)品系列。

GENERAL DESCRIPTION

The AD9520-21 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.02 GHz to 2.335 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.

The AD9520 serial interface supports both SPI and I2C? ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.

The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs.

FEATURES

Low phase noise, phase-locked loop (PLL)

On-chip VCO tunes from 2.02 GHz to 2.335 GHz

Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz

1 differential or 2 single-ended reference inputs

Accepts CMOS, LVDS, or LVPECL references to 250 MHz

Accepts 16.67 MHz to 33.3 MHz crystal for reference input

Optional reference clock doubler

Reference monitoring capability

Auto and manual reference switchover/holdover modes, with selectable revertive/nonrevertive switching

Glitch-free switchover between references

Automatic recovery from holdover

Digital or analog lock detect, selectable

Optional zero delay operation

Twelve 1.6 GHz LVPECL outputs divided into 4 groups

Each group of 3 has a 1-to-32 divider with phase delay

Additive output jitter as low as 225 fs rms

Channel-to-channel skew grouped outputs <16 ps

Each LVPECL output can be configured as 2 CMOS outputs (for fOUT ≤ 250 MHz)

Automatic synchronization of all outputs on power-up

Manual synchronization of outputs as needed

SPI- and I2C-compatible serial control port

64-lead LFCSP

Nonvolatile EEPROM stores configuration settings

APPLICATIONS

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols

Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

ATE and high performance instrumentation

Broadband infrastructures