AD9549ABCPZ集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)規(guī)格書(shū)PDF中文資料

AD9549ABCPZ屬于集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9549ABCPZ應(yīng)用特定時(shí)鐘/定時(shí)專用時(shí)鐘和計(jì)時(shí) IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時(shí)間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計(jì)環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤(pán)播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂(lè)總線等。

GENERAL DESCRIPTION

The AD9549 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9549 generates an output clock, synchronized to one of two external input references. The external references may contain significant time jitter, also specified as phase noise. Using a digitally controlled loop and holdover circuitry, the AD9549 continues to generate a clean (low jitter), valid output clock during a loss of reference condition, even when both references have failed.

The AD9549 operates over an industrial temperature range of ?40°C to +85°C.

FEATURES

Flexible reference inputs

Input frequencies: 8 kHz to 750 MHz

Two reference inputs

Loss of reference indicators

Auto and manual holdover modes

Auto and manual switchover modes

Smooth A-to-B phase transition on outputs

Excellent stability in holdover mode

Programmable 16 + 1-bit input divider, R

Differential HSTL clock output

Output frequencies to 750 MHz

Low jitter clock doubler for frequencies of >400 MHz

Single-ended CMOS output for frequencies of <150 MHz

Programmable digital loop filter (<1 Hz to ~100 kHz)

High speed digitally controlled oscillator (DCO) core

Direct digital synthesizer (DDS) with integrated 14-bit DAC

Excellent dynamic performance

Programmable 16 + 1-bit feedback divider, S

Software controlled power-down

Available 64-lead LFCSP package

APPLICATIONS

Network synchronization

Reference clock jitter cleanup

SONET/SDH clocks up to OC-192, including FEC

Stratum 3/3E reference clocks

Wireless base station, controllers

Cable infrastructure

Data communications