AD9608-125EBZ開(kāi)發(fā)板套件編程器的評(píng)估板-模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書(shū)PDF中文資料

AD9608-125EBZ屬于開(kāi)發(fā)板套件編程器的評(píng)估板-模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9608-125EBZ評(píng)估板 - 模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器 (ADC) 評(píng)估板是預(yù)裝有元器件的電路板，用于提供特定 ADC 或器件工作實(shí)例。特定板上的 A/D 轉(zhuǎn)換器數(shù)量從 3 到 32 不等，每秒采樣率從 2.5 kHz 到 26 GHz 不等，輸入電壓范圍從 0 到 8 Vp-p。

GENERAL DESCRIPTION

The AD9608 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC) that features a high performance sample-and-hold circuit and an on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

FEATURES

1.8 V analog supply operation

1.8 V CMOS or 1.8 V LVDS output

SNR = 61.7 dBFS at 70 MHz

SFDR = 85 dBc at 70 MHz

Low power: 71 mW/channel ADC core at 125 MSPS

Differential analog input with 650 MHz bandwidth

IF sampling frequencies to 200 MHz

On-chip voltage reference and sample-and-hold circuit

2 V p-p differential analog input

DNL = ±0.13 LSB

Serial port control options

Offset binary, Gray code, or twos complement data format

Optional clock duty cycle stabilizer

Integer 1-to-8 input clock divider

Data output multiplex option

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out with programmable clock and data alignment