AD9627ABCPZ-125集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD9627ABCPZ-125屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導體技術(shù)有限公司制造生產(chǎn)的AD9627ABCPZ-125模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

GENERAL DESCRIPTION

The AD9627 is a dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS analog-to-digital converter (ADC). The AD9627 is designed to support communications applications where low cost, small size, and versatility are desired.

FEATURES

?? SNR = 69.4 dBc (70.4 dBFS) to 70 MHz @ 125 MSPS

?? SFDR = 85 dBc to 70 MHz @ 125 MSPS

?? Low power: 750 mW @ 125 MSPS

?? SNR = 69.2 dBc (70.2 dBFS) to 70 MHz @ 150 MSPS

?? SFDR = 84 dBc to 70 MHz @ 150 MSPS

?? Low power: 820 mW @ 150 MSPS

?? 1.8 V analog supply operation

?? 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS

????? output supply

?? Integer 1-to-8 input clock divider

?? IF sampling frequencies to 450 MHz

?? Internal ADC voltage reference

?? Integrated ADC sample-and-hold inputs

?? Flexible analog input range: 1 V p-p to 2 V p-p

?? Differential analog inputs with 650 MHz bandwidth

?? ADC clock duty cycle stabilizer

?? 95 dB channel isolation/crosstalk

?? Serial port control

?? User-configurable, built-in self-test (BIST) capability

?? Energy-saving power-down modes

?? Integrated receive features

?? Fast detect/threshold bits

?? Composite signal monitor

APPLICATIONS

?? Communications

?? Diversity radio systems

?? Multimode digital receivers (3G)

????? GSM, EDGE, WCDMA,

????? CDMA2000, WiMAX, TD-SCDMA

?? I/Q demodulation systems

?? Smart antenna systems

?? General-purpose software radios

?? Broadband data applications