AD9645BCPZ-125集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書(shū)PDF中文資料

AD9645BCPZ-125屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9645BCPZ-125模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對(duì)模擬信號(hào)進(jìn)行采樣，例如由麥克風(fēng)采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號(hào)。一般來(lái)說(shuō)，數(shù)字輸出是二進(jìn)制補(bǔ)碼二進(jìn)制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進(jìn)行選擇。

GENERAL DESCRIPTION

The AD9645 is a dual, 14-bit, 80 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

FEATURES

1.8 V supply operation

Low power: 122 mW per channel at 125 MSPS with scalable

power options

SNR = 74 dBFS (to Nyquist)

SFDR = 91 dBc at 70 MHz

DNL = ±0.65 LSB (typical); INL = ±1.5 LSB (typical)

Serial LVDS (ANSI-644, default) and low power, reduced

range option (similar to IEEE 1596.3)

650 MHz full power analog bandwidth

2 V p-p input voltage range

Serial port control

Full chip and individual channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Clock divider

Programmable output clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

Broadband data applications

Battery-powered instruments

Handheld scope meters

Portable medical imaging and ultrasound

Radar/LIDAR