AD9674集成電路（IC）的模擬前端（AFE）規(guī)格書PDF中文資料

AD9674屬于集成電路（IC）的模擬前端（AFE）。由亞德諾半導體技術有限公司制造生產的AD9674模擬前端（AFE）模擬前端 (AFE) 是一種用于信號調節(jié)的半導體器件，由模擬放大器、運算放大器、濾波器和集成電路構成。這種可配置功能塊能連接各種傳感器。分辨率范圍從 8 位至 42 位不等，通道數(shù)范圍為 1 至 256 個。

GENERAL DESCRIPTION

The AD9674 is designed for low cost, low power, small size, and ease of use for medical ultrasound. It contains eight channels of a VGA with an LNA, a CW harmonic rejection I/Q demodulator with programmable phase rotation, an AAF, an ADC, a digital HPF, and RF decimation by 2.

FEATURES

8 channels of LNA, VGA, AAF, ADC, and digital RF decimator

Low power: 150 mW per channel, TGC mode, 40 MSPS;

62.5 mW per channel, CW mode; <30 mW in power-down

Time gain compensation (TGC) channel input referred noise:

0.82 nV/√Hz, maximum gain

Flexible power-down modes

Fast recovery from low power standby mode: <2 μs

Low noise preamplifier (LNA)

Input referred noise voltage: 0.78 nV/√Hz, gain = 21.6 dB

Programmable gain: 15.6 dB/17.9 dB/21.6 dB

0.1 dB compression: 1.00 V p-p/

0.75 V p-p/0.45 V p-p

Flexible active input impedance matching

Variable gain amplifier (VGA)

Attenuator range: 45 dB, linear in dB gain control

Postamplifier gain (PGA): 21 dB/24 dB/27 dB/30 dB

Antialiasing filter (AAF)

Programmable second-order low-pass filter (LPF) from 8 MHz

to 18 MHz or 13.5 MHz to 30 MHz and high-pass filter (HPF)

Analog-to-digital converter (ADC)

Signal-to-noise ratio (SNR): 75 dB, 14 bits up to 125 MSPS

Configurable serial low voltage differential signaling (LVDS)

Continuous wave (CW) Doppler mode harmonic rejection I/Q

demodulator

Individual programmable phase rotation

Dynamic range per channel: >160 dBFS/√Hz

Close in SNR: 156 dBc/√Hz, 1 kHz offset, ?3 dBFS input

Radio frequency (RF) digital HPF and decimation by 2

10 mm × 10 mm, 144-ball CSP_BGA

APPLICATIONS

Medical imaging/ultrasound

Nondestructive Testing (NDT)