AD9707BCPZRL7集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書PDF中文資料

AD9707BCPZRL7屬于集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9707BCPZRL7數(shù)模轉(zhuǎn)換器（DAC）數(shù)模轉(zhuǎn)換器（DAC、D/A、D2A 或 D 轉(zhuǎn) A）可將數(shù)字信號轉(zhuǎn)換為緩沖或無緩沖的模擬電壓或電流。DAC 架構(gòu)是否適合特定應(yīng)用，要取決于分辨率和采樣頻率。DAC 通常用于音樂播放器，將數(shù)字?jǐn)?shù)據(jù)流轉(zhuǎn)換為模擬音頻流。它們還用于電視和手機(jī)，將數(shù)字視頻數(shù)據(jù)轉(zhuǎn)換為模擬視頻信號，再連接到屏幕驅(qū)動器，以顯示單色或彩色圖像。

GENERAL DESCRIPTION

The AD9704/AD9705/AD9706/AD9707 are the fourthgeneration family in the TxDAC series of high performance, CMOS digital-to-analog converters (DACs). This pin-compatible, 8–/10–/12–/14–bit resolution family is optimized for low power operation, while maintaining excellent dynamic performance.

FEATURES

Pin-compatible family

Low power member of pin-compatible TxDAC product family

Power dissipation @ 3.3 V 22 mW @ 10 MSPS 25 mW @ 25 MSPS 30 mW @ 50 MSPS

Sleep mode: 3.1 mW @ 3.3 V

Supply voltage: 1.7 V to 3.6 V

SFDR to Nyquist AD9707: 84 dBc @ 5 MHz output AD9707: 83 dBc @ 10 MHz output AD9707: 75 dBc @ 20 MHz output

AD9707 NSD @ 10 MHz output, 125 MSPS: ?147 dBc/Hz

Differential current outputs: 1 mA to 5 mA

Data format: twos complement or straight binary

On-chip 1.0 V reference

CMOS-compatible digital interface

Edge-triggered latches

Clock input: single-ended and differential

Output common mode: adjustable 0 V to 1.2 V

Power-down mode < 2 mW @ 3.3 V (SPI? controllable)

Serial peripheral interface (SPI)

Self-calibration

32-lead LFCSP_VQ, Pb-free package